{"id":36,"date":"2025-10-21T03:50:13","date_gmt":"2025-10-21T03:50:13","guid":{"rendered":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/?page_id=36"},"modified":"2025-10-21T03:58:58","modified_gmt":"2025-10-21T03:58:58","slug":"design-of-computing-systems","status":"publish","type":"page","link":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/?page_id=36","title":{"rendered":"Design of Computing Systems"},"content":{"rendered":"\n<div class=\"wp-block-group alignwide is-layout-flow wp-block-group-is-layout-flow\">\n<p class=\"is-style-text-subtitle is-style-text-subtitle--1 wp-block-paragraph\">Parter Project 1: Pipelined processor on Altera Cyclone V FPGA using Intel Quartus Prime software <\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-group alignwide is-layout-flow wp-block-group-is-layout-flow\">\n<ul class=\"wp-block-list\">\n<li>Objective: Substantially improve single-cycle processor design, such that running the recursive 6! program runs in under 500ns.<\/li>\n\n\n\n<li>Key requirements\n<ul class=\"wp-block-list\">\n<li>Substantially reduce the number of clock cycles the processor takes to execute 6!<\/li>\n\n\n\n<li>Pipeline processor into 3 stages and handle data hazards<\/li>\n\n\n\n<li>Simulate (debug) with ModelSim Altera<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Project management approach: Planning meeting with partner, then daily work time in lab<\/li>\n\n\n\n<li>Challenges encountered\n<ul class=\"wp-block-list\">\n<li>Slow compile time <img decoding=\"async\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAP\/\/\/wAAACH5BAEAAAAALAAAAAABAAEAAAICRAEAOw==\">\u2192 difficult to rapidly debug<\/li>\n\n\n\n<li>Few optimizations left to be made, as single cycle was already optimized (ran at 100Mhz)<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Outcome\n<ul class=\"wp-block-list\">\n<li>Successfully reduced the number of clock cycles the processor takes from 100+ to 72 (minimum)<\/li>\n\n\n\n<li>Execution runtime @ 160MHz was 450ns, well under requirements<\/li>\n\n\n\n<li>Implemented hazard detection, data forwarding, and branch prediction to deal with data hazards.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/div>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"615\" src=\"https:\/\/ngcavallo.digitalscholarship.brown.edu\/wp-content\/uploads\/2025\/10\/Screenshot-2025-10-20-at-11.45.10-PM-1024x615.png\" alt=\"\" class=\"wp-image-43\" srcset=\"https:\/\/ngcavallo.digitalscholarship.brown.edu\/wp-content\/uploads\/2025\/10\/Screenshot-2025-10-20-at-11.45.10-PM-1024x615.png 1024w, https:\/\/ngcavallo.digitalscholarship.brown.edu\/wp-content\/uploads\/2025\/10\/Screenshot-2025-10-20-at-11.45.10-PM-300x180.png 300w, https:\/\/ngcavallo.digitalscholarship.brown.edu\/wp-content\/uploads\/2025\/10\/Screenshot-2025-10-20-at-11.45.10-PM-768x461.png 768w, https:\/\/ngcavallo.digitalscholarship.brown.edu\/wp-content\/uploads\/2025\/10\/Screenshot-2025-10-20-at-11.45.10-PM-1536x922.png 1536w, https:\/\/ngcavallo.digitalscholarship.brown.edu\/wp-content\/uploads\/2025\/10\/Screenshot-2025-10-20-at-11.45.10-PM.png 1776w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<div class=\"wp-block-group alignwide is-layout-flow wp-block-group-is-layout-flow\">\n<p class=\"is-style-text-subtitle is-style-text-subtitle--2 wp-block-paragraph\">Final Partner Project: Game Design<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Objective: Use VGA-FPGA interface module and I\/O to create a game that is coded entirely in RISC-V assembly, and integrate it with single-cycle processor<\/li>\n\n\n\n<li>Key requirements\n<ul class=\"wp-block-list\">\n<li>Implement memory controller to interface with VGA and I\/O<\/li>\n\n\n\n<li>Debug only using on-board RAM (simulation not possible)<\/li>\n\n\n\n<li>Limited ASCII sprites and colors (12 bit RGB)<\/li>\n\n\n\n<li>Code game in software (RISC-V assembly), then hex dump into instruction memory of single-cycle processor<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Project management approach: Planning meeting with partner, then daily work time in lab<\/li>\n\n\n\n<li>Challenges encountered\n<ul class=\"wp-block-list\">\n<li>Slow compile time <img decoding=\"async\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAP\/\/\/wAAACH5BAEAAAAALAAAAAABAAEAAAICRAEAOw==\">\u2192 difficult to rapidly debug<\/li>\n\n\n\n<li>Inexplicable bugs with VGA-FPGA interface module, possibly to do with inconsistent reference clocks<\/li>\n\n\n\n<li>Difficult to code game purely in RISC-V Assembly, especially with limited instruction set \u2192 only use load word and store word to interface with both I\/O, VGA, and on-board RAM if game state needs to be referenced<\/li>\n\n\n\n<li>Additional instructions were implemented \u2013&gt; BGE (branch if greater than or equal to) and BE (branch if equal to)<\/li>\n\n\n\n<li>Used button polling to continuously monitor if buttons\/switches were being pressed.<\/li>\n\n\n\n<li>Memory addresses in compiler were word addressable while memory addresses in on-board RAM were byte addressable, making managing memory location and accessing game state extremely difficult<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Outcome: Successfully created drawing game that used push buttons, switches, and VGA module to draw and erase.<\/li>\n<\/ul>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Parter Project 1: Pipelined processor on Altera Cyclone V FPGA using Intel Quartus Prime software Final Partner Project: Game Design<\/p>\n","protected":false},"author":1,"featured_media":42,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-36","page","type-page","status-publish","has-post-thumbnail","hentry"],"_links":{"self":[{"href":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/index.php?rest_route=\/wp\/v2\/pages\/36","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=36"}],"version-history":[{"count":3,"href":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/index.php?rest_route=\/wp\/v2\/pages\/36\/revisions"}],"predecessor-version":[{"id":48,"href":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/index.php?rest_route=\/wp\/v2\/pages\/36\/revisions\/48"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/index.php?rest_route=\/wp\/v2\/media\/42"}],"wp:attachment":[{"href":"https:\/\/ngcavallo.digitalscholarship.brown.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=36"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}