Parter Project 1: Pipelined processor on Altera Cyclone V FPGA using Intel Quartus Prime software
- Objective: Substantially improve single-cycle processor design, such that running the recursive 6! program runs in under 500ns.
- Key requirements
- Substantially reduce the number of clock cycles the processor takes to execute 6!
- Pipeline processor into 3 stages and handle data hazards
- Simulate (debug) with ModelSim Altera
- Project management approach: Planning meeting with partner, then daily work time in lab
- Challenges encountered
- Slow compile time
→ difficult to rapidly debug - Few optimizations left to be made, as single cycle was already optimized (ran at 100Mhz)
- Slow compile time
- Outcome
- Successfully reduced the number of clock cycles the processor takes from 100+ to 72 (minimum)
- Execution runtime @ 160MHz was 450ns, well under requirements
- Implemented hazard detection, data forwarding, and branch prediction to deal with data hazards.
Final Partner Project: Game Design
- Objective: Use VGA-FPGA interface module and I/O to create a game that is coded entirely in RISC-V assembly, and integrate it with single-cycle processor
- Key requirements
- Implement memory controller to interface with VGA and I/O
- Debug only using on-board RAM (simulation not possible)
- Limited ASCII sprites and colors (12 bit RGB)
- Code game in software (RISC-V assembly), then hex dump into instruction memory of single-cycle processor
- Project management approach: Planning meeting with partner, then daily work time in lab
- Challenges encountered
- Slow compile time → difficult to rapidly debug
- Inexplicable bugs with VGA-FPGA interface module, possibly to do with inconsistent reference clocks
- Difficult to code game purely in RISC-V Assembly, especially with limited instruction set → only use load word and store word to interface with both I/O, VGA, and on-board RAM if game state needs to be referenced
- Additional instructions were implemented –> BGE (branch if greater than or equal to) and BE (branch if equal to)
- Used button polling to continuously monitor if buttons/switches were being pressed.
- Memory addresses in compiler were word addressable while memory addresses in on-board RAM were byte addressable, making managing memory location and accessing game state extremely difficult
- Slow compile time
- Outcome: Successfully created drawing game that used push buttons, switches, and VGA module to draw and erase.